ASIC Design and/or Verification Engineer

Synopsys Ver Empresa

Não especificado
Licenciatura

As a member of the Synopsys mixed signal IP team you will work with global teams to define and develop testplan, testbench and testcases to verify mixed signal (digital and analog) designs.

Position Responsibilities:

  • Generates verification specifications.
  • Determines test bench design and test cases.
  • Evaluates and exercises various aspects of the development flow which may include such items as Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, and verification coverage metrics.
  • Generates documentation for test plans, verification environments, and usage.
  • Participate in evaluation and troubleshooting of digital and mixed signal designs.

Requirements:

  • Candidate should have a strong desire to learn and explore new technologies.
  • Demonstrates good communication skills in English.
  • Has a strong desire to learn and explore new technologies.
  • Follows standard practices and specific, outlined, and detailed procedures in analyzing situations or data from which answers can be readily obtained.
  • Demonstrates good analysis and problem-solving skills.
  • Prior knowledge and experience of CAD tool for development are required.
  • Working knowledge of Bluetooth wireless technology
  • Working knowledge of of Verilog and SystemVerilog.
  • Understanding of verification methodology such as UVM is a plus.
  • Typically requires a minimum of 2 years of related experience in verification.

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