Manager, ASIC Digital Design Engineer

Synopsys Ver Empresa

Não especificado
Licenciatura

As a senior member of the Synopsys mixed signal IP team you will direct and guide the activities of a local technical verification team and work with global leads and teams for functional verification of mixed signal (digital and analog) designs.

Position Responsibilities:

  • Perform hands-on tasks as needed and set examples and provide technical guidance for junior team members.
  • Selects, develops, and evaluates personnel to ensure the efficient operation of the function.
  • Follows processes and operational policies in selecting methods and techniques for obtaining solutions.
  • Supervise and delegate team assignments, evaluates results of team efforts to assure accomplishment of technical objectives.
  • Prepare and present reports outlining the progress/outcome of technical projects for reviews and makes recommendations for actions necessary to achieve desired results.
  • Interacts with senior internal personnel, functional peer group managers, normally involving matters between functional areas.
  • Leads a cooperative effort among members and other global teams.

Requirements:

  • Requires strong hands-on IC design/verification experiences and knowledge of all phases of the IC design process
  • Good working knowledge of Verilog/SystemVerilog languages & modern verification methodology such as UVM.
  • Work experiences or working knowledge of memory related protocols, e.g. HBM, DDR, DFI.
  • Good communication & presentation skills in English.
  • Related experiences as a team lead or manager.
  • Typically requires a minimum of 5 years of related experience in verification.

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