Senior Mixed-Signal Design Engineer

S3 Group Ver Empresa

Não especificado
Licenciatura

Reporting to the Group Manager in our Lisbon Office, we are looking for Senior Analog/Mixed-Signal Design Engineers. The successful candidates will be working within a team of experienced design engineers undertaking system architecture, RF and Analog Design, verification and implementation of complex RF/Analog/Digital SoC solutions. The project tasks may require study, design and layout of analog/mixed-signal blocks. Working in teams of design/layout to successfully design state-of-the art ASICs.

To be considered for this position you must have:

  • A graduate or post-graduate qualification in Electronic Engineering.
  • At least 8 years’ experience in CMOS analog circuit design.
  • Expertise in the design of some of the following mixed-signal circuits: ADCs, DACs, PLLs, power management.
  • User-experience in complete IC design flows.
  • A track record of successful analog design project completion and delivery.
  • Technical curiosity and a good understanding of the latest developments in the industry and of leading-edge design techniques.
  • Excellent problem solving skills.
  • Strong analytical skills.
  • Good leadership skills.
  • An ability to incorporate business influences in engineering decisions.
  • Strong oral and written communication skills.
  • Short-term travel will be occasionally required.
  • Experience in the following Areas would be a distinct advantage.
  • At least 5 years’ direct experience in converting customer requirements into detailed technical specifications.

Expertise in complete IC Design Flows would be an advantage: Analog IC Architecture Design and Modelling; IP Evaluation and Selection, Analog/Digital partitioning in mixed-signal systems; high-speed data communications / SERDES; modelling of Analog Systems.

Expertise in the use of the following CAD Tools would be an advantage: Spectre Simulator, Cadence Virtuoso Schematic/Layout, Verilog-AMS, NCSIM, Mentor Calibre DRC/LVS.
Expertise in the design of some of the following: PLLs and Oscillators, Baseband Filters, Data Converters and Power Management Blocks.

Die-size estimation and modelling the trade-offs between functionality and die-size and package selection.
Familiarity with the major semiconductor process nodes and their relative advantages and disadvantages, especially in the context of analog design implementation impacts.

Technical curiosity and a good understanding of the latest developments in the industry and of leading-edge design techniques, willingness and ability to quickly adopt new technologies.

An ability to incorporate business influences in engineering decisions and an understanding of the commercial implications of technical decisions and vice versa.

Travel will be required, mostly to/from S3 Group engineering offices, but also to our worldwide customer locations.

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